Publications HAL de Wendelin,SERWE de la collection LIG
titre
Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits
auteur
Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe
article
ASYNC'18 - 24th IEEE International Symposium on Asynchronous Circuits and Systems , May 2018, Vienne, Austria
titre
TESTOR: A Modular Tool for On-the-Fly Conformance Test Case Generation
auteur
Lina Marsso, Radu Mateescu, Wendelin Serwe
article
TACAS 2018 - 24th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Apr 2018, Thessaloniki, Greece. pp.211-228, ⟨10.1007/978-3-319-89963-3_13⟩
titre
Using LNT Formal Descriptions for Model-Based Diagnosis
auteur
Birgit Hofer, Radu Mateescu, Wendelin Serwe, Franz Wotawa
article
DX 2018 - 29th International Workshop on Principles of Diagnosis, Aug 2018, Warsaw, Poland. pp.1-8
titre
The Unheralded Value of the Multiway Rendezvous: Illustration with the Production Cell Benchmark
auteur
Hubert Garavel, Wendelin Serwe
article
2nd Workshop on Models for Formal Analysis of Real Systems, Apr 2017, Uppsala, Sweden. pp.230 - 270, ⟨10.4204/EPTCS.244.10⟩
titre
From LOTOS to LNT
auteur
Hubert Garavel, Frédéric Lang, Wendelin Serwe
article
Joost-Pieter Katoen; Rom Langerak; Arend Rensink. ModelEd, TestEd, TrustEd - Essays Dedicated to Ed Brinksma on the Occasion of His 60th Birthday, 10500, Springer, pp.3 - 26, 2017, Lecture Notes in Computer Science, 978-3-319-68270-9. ⟨10.1007/978-3-319-68270-9_1⟩
titre
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis
auteur
Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris Myers
article
Science of Computer Programming, Elsevier, 2016, ⟨10.1016/j.scico.2016.01.002⟩
titre
Formal Specification and Verification of Fully Asynchronous Implementations of the Data Encryption Standard
auteur
Wendelin Serwe
article
Proceedings of the first Workshop on Models for Formal Analysis of Real Systems (MARS 2015), Nov 2015, Suva, Fiji. ⟨10.4204/EPTCS.196.6⟩
titre
Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip
auteur
Abderahman Kriouile, Wendelin Serwe
article
21th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Apr 2015, London, UK, France. pp.708--722, ⟨10.1007/978-3-662-46681-0_62⟩
titre
Formal Analysis of a Hardware Dynamic Task Dispatcher with CADP
auteur
Etienne Lantreibecq, Wendelin Serwe
article
Science of Computer Programming, Elsevier, 2014, 80, pp.130-149. ⟨10.1016/j.scico.2013.01.003⟩
titre
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip
auteur
Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris Myers
article
19th International Conference on Formal Methods for Industrial Critical Systems, FMICS 2014, Sep 2014, Florence, Italy. pp.48-62, ⟨10.1007/978-3-319-10702-8_4⟩
titre
CADP 2011: A Toolbox for the Construction and Analysis of Distributed Processes
auteur
Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe
article
International Journal on Software Tools for Technology Transfer, Springer Verlag, 2013, 15 (2), pp.89-107. ⟨10.1007/s10009-012-0244-z⟩
titre
Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip
auteur
Abderahman Kriouile, Wendelin Serwe
article
FMICS - 18th International Workshop on Formal Methods for Industrial Critical Systems, ERCIM Working Group on Formal Methods for Industrial Critical Systems (FMICS), Sep 2013, Madrid, Spain. pp.108-122
titre
Génération et manipulation d'espaces d'états distribués avec CADP : expériences sur Grid'5000
auteur
Hubert Garavel, Radu Mateescu, Wendelin Serwe
article
Conférence en Parallélisme, Architecture et Système ComPAS'2013, Jan 2013, Grenoble, France
titre
Analyse formelle du protocole ACE : cohérence de caches des systèmes sur puce
auteur
Abderahman Kriouile, Wendelin Serwe
article
École d'été Temps-Réel 2013, Aug 2013, Toulouse, France. pp.130-133
titre
Model Checking and Performance Evaluation with CADP Illustrated on Shared-Memory Mutual Exclusion Protocols
auteur
Radu Mateescu, Wendelin Serwe
article
Science of Computer Programming, Elsevier, 2012, 78 (7), pp.843-861. ⟨10.1016/j.scico.2012.01.003⟩
titre
Large-Scale Distributed Verification using CADP: Beyond Clusters to Grids
auteur
Hubert Garavel, Radu Mateescu, Wendelin Serwe
article
11th International Workshop on Parallel and Distributed Methods in verifiCation, Sep 2012, London, United Kingdom
titre
CADP : une boîte à outils pour la conception et l'analyse de systèmes distribués
auteur
Hubert Garavel, Frédéric Lang, Radu Mateescu, Gwen Salaün, Wendelin Serwe
article
Approches Formelles dans l'Assistance au Développement de Logiciels, Jan 2012, Grenoble, France. 2012
titre
CADP: A Toolbox for the Construction and Analysis of Distributed Processes
auteur
Hubert Garavel, Frédéric Lang, Radu Mateescu, Gwen Salaün, Wendelin Serwe
article
FM - 18th International Symposium on Formal Methods - 2012, Aug 2012, Paris, France
titre
CADP 2010: A Toolbox for the Construction and Analysis of Distributed Processes
auteur
Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe
article
Tools and Algorithms for the Construction and Analysis of Systems - TACAS 2011, Mar 2011, Saabrucken, Germany
titre
Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit using CADP
auteur
Etienne Lantreibecq, Wendelin Serwe
article
Formal Methods for Industrial Critical Systems, 2011, Trento, Italy
titre
A Study of Shared-Memory Mutual Exclusion Protocols using CADP
auteur
Radu Mateescu, Wendelin Serwe
article
15th International Workshop on Formal Methods for Industrial Critical Systems '2010, Sep 2010, Antwerp, Belgium
titre
Ten Years of Performance Evaluation for Concurrent Systems Using CADP
auteur
Nicolas Coste, Hubert Garavel, Holger Hermanns, Frédéric Lang, Radu Mateescu, Wendelin Serwe
article
4th International Symposium on Leveraging Applications of Formal Methods, Verification and Validation ISoLA 2010, Oct 2010, Amirandes, Heraclion, Greece. pp.128-142
titre
On the Semantics of Communicating Hardware Processes and their Translation into LOTOS for the Verification of Asynchronous Circuits with CADP
auteur
Hubert Garavel, Gwen Salaun, Wendelin Serwe
article
Science of Computer Programming, Elsevier, 2009
titre
Towards Performance Prediction of Compositional Models in Industrial GALS Designs
auteur
Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe
article
Computer Aided Verification, Saddek Bensalem, 2009, Grenoble, France
titre
Verification of an Industrial SystemC/TLM Model using LOTOS and CADP
auteur
Hubert Garavel, Claude Helmstetter, Olivier Ponsini, Wendelin Serwe
article
7th ACM-IEEE International Conference on Formal Methods and Models for Codesign MEMOCODE'2009, Jul 2009, Cambridge, MA, United States
titre
A Schedulerless Semantics of TLM Models Written in SystemC via Translation into LOTOS
auteur
Olivier Ponsini, Wendelin Serwe
article
Formal Methods, May 2008, Turku, Finland
titre
Formal Verification of CHP Specifications with CADP - Illustration on an Asynchronous Network-on-Chip
auteur
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
article
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC 2007, Mar 2007, Berkeley, California, United States
titre
CADP 2006: A Toolbox for the Construction and Analysis of Distributed Processes
auteur
Hubert Garavel, Frédéric Lang, Radu Mateescu, Wendelin Serwe
article
Computer Aided Verification (CAV'2007), Jul 2007, Berlin, Germany. pp.158-163
titre
Translating Hardware Process Algebras into Standard Process Algebras : Illustration with CHP and LOTOS
auteur
Gwen Salaün, Wendelin Serwe
article
RR-5666, INRIA. 2005, pp.25